
1
226214fc
LTC2262-14
For more information www.linear.com/LTC2262-14
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
14-Bit, 150Msps
Ultralow Power 1.8V ADC
n
Communications
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Cellular Base Stations
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Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
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Nondestructive Testing
n
72.8dB SNR
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88dB SFDR
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Low Power: 149mW
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Single 1.8V Supply
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CMOS, DDR CMOS or DDR LVDS Outputs
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Selectable Input Ranges: 1VP-P to 2VP-P
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800MHz Full-Power Bandwidth S/H
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Optional Data Output Randomizer
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Optional Clock Duty Cycle Stabilizer
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Shutdown and Nap Modes
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Serial SPI Port for Configuration
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Pin Compatible 14-Bit and 12-Bit Versions
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40-Pin (6mm
× 6mm) QFN Package
designed for digitizing high frequency, wide dynamic
range signals. The LTC2262-14 is perfect for demanding
communications applications with AC performance that
includes 72.8dB SNR and 88dB spurious free dynamic
range (SFDR). Ultralow jitter of 0.17psRMS allows unders-
amplingofIFfrequencieswithexcellentnoiseperformance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal)andnomissingcodesovertemperature.Thetransition
noise is a low 1.2LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
LTC2262-14 2-Tone FFT,
fIN = 68MHz and 69MHz
–
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
150MHz
CLOCK
ANALOG
INPUT
226214 TA01a
CMOS
OR
LVDS
1.2V
TO 1.8V
1.8V
VDD
OVDD
OGND
GND
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE
(dBFS) –50
–30
–40
–20
–10
0
226214 TA01b
0
10
20
30
40
50
70
60
L
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Technology Corporation. All other trademarks are the property of their respective owners.